Embodiments of the present disclosure relate to a non-volatile semiconductor device, and more particularly to a non-volatile semiconductor memory device configured to improve a structure of interconnection lines for a decoder in a semiconductor memory device having a PUC (Peri Under Cell) structure in which the decoder is located below a cell region.
Semiconductor memories are largely classified into volatile memory devices and non-volatile memory devices. A non-volatile memory device is a memory device capable of preserving stored data even when power supply interrupts. Various non-volatile memory devices such as flash memories have been widely used.
Since the integration enhancement of a two-dimensional (2D) non-volatile memory device in which a single-layered memory cell is formed over a semiconductor substrate is limited, there has been recently introduced a 3D non-volatile memory device in which memory cells are stacked along a channel layer vertically protruding from the semiconductor substrate.
The 3D non-volatile memory devices are largely classified into a first type of 3D non-volatile memory device having a line-shaped channel layer and a second type of 3D non-volatile memory device having a U-shaped channel layer. The 3D non-volatile memory device having the line-shaped channel layer includes a bit line and a source line respectively formed above and below stacked memory cells. In the 3D non-volatile memory device having the U-shaped channel layer, both of the bit line and the source line are disposed over stacked memory cells.
In addition, a PUC (Peri Under Cell) structure has recently been proposed in which a decoder is located below the cell region of a 3D non-volatile memory device. In a conventional PUC structure, metal lines are formed over and under the cell region, which are referred to as “upper metal line(s)” and “under metal line(s),” respectively. A decoder and a control circuit for supplying signals and power to the decoder are interconnected through the under-metal line.
However, since the under-metal line is formed of a material having higher resistance than an upper metal line, time for data or power transfer through the under metal line significantly increases and thus the operation characteristics of a chip are deteriorated. Additionally, the chip size unavoidably increases due to the presence of such under metal lines.